1. Field of the invention
This invention relates to an inverter logic circuit employing BiCMOS elements.
2. Description of the Prior Art
FIG. 1 shows a conventional CMOS inverter which is comprised of P and N type MOS transistors M.sub.11 and M.sub.12 having MOS transistors M.sub.13 and M.sub.14 and transistors Q.sub.1 and Q.sub.2 connected thereto.
In the CMOS inverter circuit as shown in FIG. 1, if an input signal 11 is high, the MOS transistor M.sub.12 is turned on. Then, the base of the transistor Q.sub.1 becomes low to maintain the transistor Q.sub.1 off. At the same time, the MOS transistor M.sub.13 is turned on to provide a bias to the base of the transistor Q.sub.2 and turns the transistor Q.sub.2 on, whereby the output 14 becomes low while the MOS transistor M.sub.14 is turned off to eliminate the direct driving of current through the MOS transistors M.sub.13 and M.sub.14 The MOS transistor M.sub.14 makes the base of the transistor Q.sub.2 at ground potential only when the output 14 is high.
On the other hand, if the input 11 is low, the MOS transistor M.sub.11 is turned on to provide a bias to the base of the transistor Q.sub.1 so that since the output 14 is maintained at a high level, the MOS transistor M.sub.14 is turned on.
In the prior inverter circuit, however, as the input 11 is changed from the low level, with the MOS transistor M.sub.13 off and the MOS transistor M.sub.14 on, to the high level, the transistor Q.sub.1 is turned off and the MOS transistor M.sub.13 is turned on. Thus, the MOS transistors M.sub.13 and M.sub.14 are simultaneously turned-on before the output 14 becomes low (i.e. during the high level of the output), which delays the turn-on of the transistor Q.sub.2 and adversely affects the high speed operation of the circuit.
This delay of switching time also appears when the input 11 is changed from high to low.
A further problem of prior known inverters is that they are complex which interferes with a high degree of integration.